A common requirement for an electronic circuit and particularly for electronic circuits manufactured as integrated circuits in semiconductor processes is a non-volatile memory storage element, such as a floating gate cell. Often a module such as a FLASH, EEPROM or EPROM is provided. In these circuits, the non-volatile memory is often integrated with other, customer defined logic or licensed cores and may be integrated with other predefined or macro cells such as microprocessors, digital signal processors, cores such as ARM, RISC or similar core functions, cell phone modules, and the like.
One form of non-volatile memory cells is based on so-called “floating gates”. A floating gate is a storage element which, by virtue of various program and erase mechanisms using electron transport from a channel region or terminal, can be used to store a small charge. The stored charge then may be read in a non-destructive sensing process. By sensing whether or not a charge is stored, a logic value of a “1” or a “0” may be assigned to the charge stored/not charged in the cell and thus, data may be stored and later retrieved. Using a control gate and placing various potential voltages on the control gate and drain and source regions of the floating gate device, the stored charge may be programmed and erased. By fabricating many thousands of these cells in an area, a storage module that retains the stored data when power is removed or lost from the integrated circuit is provided. For battery powered devices such as cell phones and PDAs, the floating gate non-volatile memory cells may be used to store critical information including system settings, phone numbers, contact information, photographs, sound recordings and the like that the user wants to keep permanently stored. Unlike conventional volatile memory such as dynamic RAM (DRAM), the non-volatile memory cells do not lose their stored state when power is lost (for example, when the battery dies on a battery powered device) or is removed.
Floating gates are typically provided as a part of a transistor structure. A control gate is coupled to a gate terminal and overlies, at least in part, the floating gate. The floating gate is electrically isolated from the control gate and also from the substrate, hence the name “floating”. A source and drain area are formed, typically by doping areas of the substrate, and are provided and electrical connections to those areas are provided so that a channel region underlies the floating gate. By providing different electrical potentials on the control gate, and source and drain regions, electrons can be forced into the floating gate to program the cell. Also, by applying appropriate potentials, the electrons can be removed from the floating gate to erase the cell. The presence of the stored charge can be determined by reading the cell, e.g., by providing an appropriate potential on the control gate and observing current flow. A programmed cell has a different response than an erased cell. By observing the response to the cell to a read potential, the presence of a stored or non stored charge can be detected. In this manner the floating gate transistor acts as a non volatile storage cell.
FIG. 1 depicts a known split gate floating gate cell structure. In this exemplary example, the floating gate transistors are formed in pairs with certain common or shared terminals that will be described in further detail below.
In the cross section illustrated in FIG. 1, two floating gate cell devices 14 and 16 are illustrated in floating gate structure 10 sharing a common source region 23 in a semiconductor substrate 11. The substrate 11 is typically used to form an integrated circuit having many other devices on it, including additional floating gate cells, DRAM, SRAM cells, registers, logic gates, processors, mixed signal and analog circuits, and input/output devices such as buffers and drivers. Substrate 11 may be silicon, doped silicon, or it may be an epitaxial semiconductor layer such as a silicon-on-insulator (SOI) layer. Substrate 11 may also be of gallium arsenide (GaAs) or other semiconductor materials. A thin gate oxide 12 is formed over the substrate. Again, this may be formed as a thermal oxide such as silicon dioxide, although other gate oxides and gate dielectrics could be used. Floating gates 13 are formed and patterned over the thin gate oxide 12. These floating gates 13 are typically formed of a conductive gate material such as polysilicon or doped polysilicon. Because these gates are electrically isolated from other terminals of the device, they are referred to as “floating gates”. A dielectric layer is formed over the floating gate; typically, a thin oxide nitride oxide (ONO) layer is used, such as layer 15 in the arrangement of FIG. 2, although other dielectrics are known and may be used. High K and low K dielectric materials may be used, for example.
Control gate 17 is then formed over the layer 15; again, this gate is typically formed of known gate materials such as polysilicon, doped polysilicon and other known gate conductor materials. Gate 17 is also patterned. An isolation dielectric 19, typically formed of silicon nitride (SiN) is formed over the control gate 17. Another isolation oxide layer, for example formed of tetraethyl orthosilicate (TEOS) 21, is formed over the SiN layer 19. This vertical floating gate cell stack 14 or 16 forms the floating gate devices. In the floating gate cells of FIG. 1, the vertical sides of stacks 14 and 16, referred to as the “sidewalls”, are shown with a sidewall oxide 25 formed over them. Typically, this is formed as a thermal oxide such as a high temperature oxide (HTO). Layer 25 then provides protection for the sidewalls and isolates the sides of floating gate 13 and ONO layer 15 electrically. Because ONO layer 15 is usually formed between the polysilicon floating gate 13 and the polysilicon control gate 17, the ONO layer may be referred to as “inter-poly” or “inter-poly oxide”. For the purposes of this application, the sidewalls located closer to the central common source region 23 will be referred to as “source side” sidewalls. The floating gate structures have source side sidewalls such as 33 in FIG. 1, and on the opposing side farthest away from the common source, they have drain side sidewalls such as 27.
In FIG. 1, the structure is depicted following an oxide etch step to remove the HTO oxide 25 from the substrate 11 in areas outside of the floating gate structure 10, the layer labeled PR 29 is a photo resist deposited over the structure and then patterned to protect the source side sidewalls 31 during this oxide etch step.
While the prior art floating gate structure 10 of FIG. 1 provides basic operability, in practical devices, some problems arise using this structure. A problem with reverse tunnel disturbs (RTD) has been found. In RTD sensitive circuit devices, when one floating gate cell is erased or programmed, another floating gate cell device, which is not selected and therefore not intended to be altered, has a “disturb” and charge is lost erroneously. This disturb can happen when the bias on a cell select line capacitively couples to the control gate, and the floating gate erroneously receives a voltage. In fabricating floating gate structures such as that in FIG. 1, non-uniform sidewall oxide has been observed in the areas indicated by circles 24. This thinning oxide profile (that is, in some cells, the sidewall oxide is incorrectly formed with thinned sidewall areas) results in a significant RTD effect during operation of the devices. If the RTD effect that occurs becomes sufficiently severe, the floating gate cell will not retain stored charge properly and thus, the finished integrated circuit devices may not be used.
Thus, there is a continuing need for an improved floating gate cell structure that has enhanced immunity to RTD effects. The improved floating gate cell structure and methods for fabricating the structure should remain compatible with existing and future semiconductor processes for fabricating integrated circuits, without adding significant steps or added costs.